1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device which has a diode and a capacitor.
2. Background of the Invention
As a prior-art semiconductor device, a high-speed bipolar memory cell of a circuit structure shown in FIG. 1 has been proposed in Japanese Laid-Open Patent Application No. 53-43485 which is incorporated herein by reference with regard to the state of the art in this area. This memory cell includes features that diodes D.sub.1, D.sub.2 are formed in parallel with load resistors R.sub.1, R.sub.2 as illustrated in the figure, and that the inherent capacitance of the diodes function as capacitors C.sub.1, C.sub.2. Owing to such arrangement, the memory cell is improved over past ones in the following respects: (1) fast switching is possible; (2) the operating margin increases; and (3) soft errors ascribable to a particles can be prevented.
In order to exploit the three advantages a capacitance of approximately 500 fF is required for each of the capacitors C.sub.1, C.sub.2. In the semiconductor device, to the end of attaining this capacitance, the inherent capacitance of the Schottky barrier diode is used as the memory cell capacitors C.sub.1 and C.sub.2, as described above.
Generally, an interface of a platinium silicide layer and a silicon layer or an interface of a palladium silicide layer and a silicon layer is employed for the Schottky barrier diode in the prior-art semiconductor device shown in FIG. 1. The capacitance obtained with such a diode in the prior art is only, at most 3.4 fF/.mu.m.sup.2 or so per unit area. Therefore, the area of the diode becomes as large as 150 .mu.m.sup.2 to the end of attaining the necessary capacitance mentioned above, and the diodes occupy about 30% of the area of the memory cell. This forms a serious hindrance to packaging the bipolar memory cells at a high density.